Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth

ABSTRACT

A gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a mask that includes an array of openings therein, and growing the underlying gallium nitride layer through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. Although dislocation defects may propagate vertically from the underlying gallium nitride layer to the grown gallium nitride layer through the mask openings, the overgrown gallium nitride layer is relatively defect free. The overgrown gallium nitride semiconductor layer may be overgrown until the overgrown gallium nitride layer coalesces on the mask, to form a continuous overgrown monocrystalline gallium nitride semiconductor layer. The gallium nitride semiconductor layer may be grown using metalorganic vapor phase epitaxy. Microelectronic devices may be formed in the overgrown gallium nitride semiconductor layer.

FEDERALLY SPONSORED RESEARCH

[0001] This invention was made with Government support under Office ofNaval Research Contact No. N00014-96-1-0765. The Government has certainrights to this invention.

FIELD OF THE INVENTION

[0002] This invention relates to microelectronic devices and fabricationmethods, and more particularly to gallium nitride semiconductor devicesand fabrication methods therefor.

BACKGROUND OF THE INVENTION

[0003] Gallium nitride is being widely investigated for microelectronicdevices including but not limited to transistors, field emitters andoptoelectronic devices. It will be understood that, as used herein,gallium nitride also includes alloys of gallium nitride such as aluminumgallium nitride, indium gallium nitride and aluminum indium galliumnitride.

[0004] A major problem in fabricating gallium nitride-basedmicroelectronic devices is the fabrication of gallium nitridesemiconductor layers having low defect densities. It is known that onecontributor to defect density is the substrate on which the galliumnitride layer is grown. Accordingly, although gallium nitride layershave been grown on sapphire substrates, it is known to reduce defectdensity by growing gallium nitride layers on aluminum nitride bufferlayers which are themselves formed on silicon carbide substrates.Notwithstanding these advances, continued reduction in defect density isdesirable.

[0005] It is also known to fabricate gallium nitride structures throughopenings in a mask. For example, in fabricating field emitter arrays, itis known to selectively grow gallium nitride on stripe or circularpatterned substrates. See, for example, the publications by coinventorNam et al. entitled “Selective Growth of GaN and Al _(0.2) Ga _(0.8) onGaN/AlN/6H-SiC(0001) Multilayer Substrates Via Organometallic VaporPhase Epitaxy”, Proceedings of the Materials Research Society, December1996, and “Growth of GaN and Al _(0.2) Ga _(0.8) N on PatterenedSubstrates via Organometallic Vapor Phase Epitaxy”, Japanese Journal ofApplied Physics., Vol. 36, Part 2, No. 5A, May 1997, pp. L-532-L535. Asdisclosed in these publications, undesired ridge growth or lateralovergrowth may occur under certain conditions.

SUMMARY OF THE INVENTION

[0006] It is therefore an object of the present invention to provideimproved methods of fabricating gallium nitride semiconductor layers,and improved gallium nitride layers so fabricated.

[0007] It is another object of the invention to provide methods offabricating gallium nitride semiconductor layers that can have lowdefect densities, and gallium nitride semiconductor layers sofabricated.

[0008] These and other objects are provided, according to the presentinvention, by fabricating a gallium nitride semiconductor layer bylaterally growing an underlying gallium nitride layer to thereby form alaterally grown gallium nitride semiconductor layer, and formingmicroelectronic devices in the laterally grown gallium nitridesemiconductor layer. In a preferred embodiment, a gallium nitridesemiconductor layer is fabricated by masking an underlying galliumnitride layer with a mask that includes an array of openings therein andgrowing the underlying gallium nitride layer through the array ofopenings and onto the mask, to thereby form an overgrown gallium nitridesemiconductor layer. Microelectronic devices may then be formed in theovergrown gallium nitride semiconductor layer.

[0009] It has been found, according to the present invention, thatalthough dislocation defects may pronagate vertically from theunderlying gallium nitride layer to the grown gallium nitride layerabove the mask openings, the overgrown gallium nitride layer isrelatively defect-free. Accordingly, high performance microelectronicdevices may be formed in the overgrown gallium nitride semiconductorlayer.

[0010] According to another aspect of the present invention, theovergrown gallium nitride semiconductor layer is overgrown until theovergrown gallium nitride layer coalesces on the mask, to form acontinuous overgrown monocrystalline gallium nitride semiconductorlayer. The overgrown layer can thus have overgrown regions of relativelylow defect in the area of coalescence and regions of relatively highdefects over the mask openings.

[0011] The gallium nitride semiconductor layer may be grown usingmetalorganic vapor phase epitaxy (MOVPE). Preferably, the openings inthe mask are stripes that are oriented along the <1{overscore (1)}00>direction of the underlying gallium nitride layer. The overgrown galliumnitride layer may be grown using triethylgallium (TEG) and ammonia (NH3)precursors at 1000-1100° C. and 45 Torr. Preferably, TEG at 13-39μmol/min and NH₃ at 1500 sccm are used in combination with 3000 sccm H₂diluent. Most preferably, TEG at 26 μmol/min, NH₃ at 1500 sccm and H₂ at3000 sccm at a temperature of 1100° C. and 45 Torr are used. Theunderlying gallium nitride layer preferably is formed on a substrate,which itself includes a buffer layer such as aluminum nitride, on asubstrate such as 6H-SiC(0001).

[0012] Gallium nitride semiconductor structures according to the presentinvention include an underlying gallium nitride layer, a lateral galliumnitride layer that extends from the underlying gallium nitride layer,and a plurality of microelectronic devices in the lateral galliumnitride layer. In a preferred embodiment, gallium nitride semiconductorstructures according to the present invention include an underlyinggallium nitride layer and a patterned layer (such as a mask) thatincludes an array of openings therein, on the underlying gallium nitridelayer. A vertical gallium nitride layer extends from the underlyinggallium nitride layer through the array of openings. A lateral galliumnitride layer extends from the vertical gallium nitride layer onto thepatterned layer, opposite the underlying gallium nitride layer. Aplurality of microelectronic devices including but not limited tooptoelectronic devices and field emitters, are formed in the lateralgallium nitride layer.

[0013] Preferably, the lateral gallium nitride layer is a continuousmonocrystalline gallium nitride semiconductor layer. The underlyinggallium nitride layer and the vertical gallium nitride layer bothinclude a predetermined defect density, and the lateral gallium nitridesemiconductor layer is of lower defect density than the predetermineddefect density. Accordingly, low defect density gallium nitridesemiconductor layers may be produced, to thereby allow the production ofhigh-performance microelectronic devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a cross-sectional view of gallium nitride semiconductorstructures according to the present invention.

[0015] FIGS. 2-5 are cross-sectional views of structures of FIG. 1during intermediate fabrication steps, according to the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0016] The present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. This invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the invention to thoseskilled in the art. In the drawings, the thickness of layers and regionsare exaggerated for clarity. Like numbers refer to like elementsthroughout. It will be understood that when an element such as a layer,region or substrate is referred to as being “on” another element, it canbe directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” another element, there are no intervening elements present.Moreover, each embodiment described and illustrated herein includes itscomplementary conductivity type embodiment as well.

[0017] Referring now to FIG. 1, gallium nitride semiconductor structuresaccording to the present invention are illustrated. The gallium nitridestructures 100 include a substrate 102. The substrate may be sapphire orgallium nitride. However, preferably, the substrate includes a6H-SiC(0001) substrate 102 a and an aluminum nitride buffer layer 102 bon the silicon carbide substrate 102 a. The aluminum nitride bufferlayer 102 b may 0.01 μm thick.

[0018] The fabrication of substrate 102 is well known to those havingskill in the art and need not be described further. Fabrication ofsilicon carbide substrates are described, for example, in U.S. Pat. Nos.4,865,685 to Palmour; Re 34,861 to Davis et al.; 4,912,064 to Kong etal. and 4,946,547 to Palmour et al., the disclosures of which are herebyincorporated herein by reference. Also, the crystallographic designationconventions used herein are well known to those having skill in the art,and need not be described further.

[0019] An underlying gallium nitride layer 104 is also included onbuffer layer 102 b opposite substrate 102 a. The underlying galliumnitride layer 104 may be between about 1.0 and 2.0 μm thick, and may beformed using heated metalorganic vapor phase epitaxy (MOVPE). Theunderlying gallium nitride layer generally has an undesired relativelyhigh defect density, for example dislocation densities of between about10⁸ and 10¹⁰ cm⁻². These high defect densities may result frommismatches in lattice parameters between the buffer layer 102 b and theunderlying gallium nitride layer 104. These high defect densities mayimpact performance of microelectronic devices formed in the underlyinggallium nitride layer 104.

[0020] Still continuing with the description of FIG. 1, a mask such as asilicon dioxide mask 106 is included on the underlying gallium nitridelayer 104. The mask 106 includes an array of openings therein.Preferably, the openings are stripes that extend along the <1{overscore(00)}> direction of the underlying gallium nitride layer 104. The mask106 may have a thickness of about 1000 Å and may be formed on theunderlying gallium nitride layer 104 using low pressure chemical vapordeposition (CVD) at 410° C. The mask 106 may be patterned using standardphotolithography techniques and etched in a buffered hydrofluoric acid(HF) solution.

[0021] Continuing with the description of FIG. 1, a vertical galliumnitride layer 108 a extends from the underlying gallium nitride layer104 and through the array of openings in the mask 106. As used herein,the term “vertical” means a direction that is orthogonal to the faces ofthe substrate 102. The vertical gallium nitride layer 108 a may beformed using metalorganic vapor phase epitaxy at about 1000-1100° C. and45 Torr. Precursors of triethygallium (TEG) at 13-39 μmol/min andammonia (NH₃) at 1500 sccm may be used in combination with a 3000 sccmH₂ diluent, to form the vertical gallium nitride layer 108 a.

[0022] Still continuing with the description of FIG. 1, the galliumnitride semiconductor structure 100 also includes a lateral galliumnitride layer 108 b that extends laterally from the vertical galliumnitride layer 108 a onto the mask 106 opposite the underlying galliumnitride layer 104. The lateral gallium nitride layer 108 b may be formedusing metalorganic vapor phase epitaxy as described above. As usedherein, the term “lateral” denotes a direction parallel to the faces ofsubstrate 102.

[0023] As shown in FIG. 1, lateral gallium nitride layer 108 b coalescesat interfaces 108 c to form a continuous monocrystalline gallium nitridesemiconductor layer 108. It has been found that the dislocationdensities in the underlying gallium nitride layer 104 generally do notpropagate laterally with the same intensity as vertically. Thus, lateralgallium nitride layer 108 b can have a relatively low defect density,for example less that 10⁴ cm⁻². Accordingly, lateral gallium nitridelayer 108 b may form device quality gallium nitride semiconductormaterial. Thus, as shown in FIG. 1, microelectronic devices 110 may beformed in the lateral gallium nitride layer 108 b.

[0024] Referring now to FIGS. 2-5, methods of fabricating galliumnitride semiconductor structures according to the present invention willnow be described. As shown in FIG. 2, an underlying gallium nitridelayer 104 is grown on a substrate 102. The substrate 102 may include a6H-SiC(0001) substrate 102 a and an aluminum nitride buffer layer 102 b.The gallium nitride layer 104 may be between 1.0 and 2.0 μm thick, andmay be grown at 1000° C. on a high temperature (1100° C.) aluminumnitride buffer layer 102 b that was deposited on 6H-SiC substrate 102 ain a cold wall vertical and inductively heated metalorganic vapor phaseepitaxy system using triethylgallium at 26 μmol/min, ammonia at 1500sccm and 3000 sccm hydrogen diluent. Additional details of this growthtechnique may be found in a publication by T. W. Weeks et al. entitled“GaN Thin Films Deposited Via Organometallic Vapor Phase Epitaxy ona(6H)-SiC(0001)Using High-Temperature Monocrystalline AlN BufferLayers”, Applied Physics Letters, Vol. 67, No. 3, Jul. 17, 1995, pp.401-403, the disclosure of which is hereby incorporated herein byreference. Other substrates, with or without buffer layers, may be used.

[0025] Still referring to FIG. 2, the underlying gallium nitride layer104 is masked with a mask 106 that includes an array of openings 107therein. The mask may comprise silicon dioxide at thickness of 1000 Åand may be deposited using low pressure chemical vapor deposition at410° C. Other masking materials may be used. The mask may be patternedusing standard photolithography techniques and etching in a buffered HFsolution. In one embodiment, the openings 107 are 3 μm-wide openingsthat extend in parallel at distances of between 3 and 40 μm and that areoriented along the <1{overscore (1)}00> direction on the underlyinggallium nitride layer 104. Prior to further processing, the structuremay be dipped in a 50% buffered hydrochloric acid (HCl) solution toremove surface oxides from the underlying gallium nitride layer 104.

[0026] Referring now to FIG. 3, the underlying gallium nitride layer 104is grown through the array of openings 107 to form vertical galliumnitride layer 108 a in the openings. Growth of gallium nitride may beobtained at 1000-1100° C. and 45 Torr. The precursors TEG at 13-39mol/min and NH3 at 1500 sccm may be used in combination with a 3000 sccmH₂ diluent. If gallium nitride alloys are formed, additionalconventional precursors of aluminum or indium, for example, may also beused. As shown in FIG. 3, the gallium nitride layer 108 a growsvertically to the top of the mask 106.

[0027] It will be understood that underlying gallium nitride layer 104may also be grown laterally without using a mask 106, by appropriatelycontrolling growth parameters and/or by appropriately patterning theunderlying gallium nitride layer 104. A patterned layer may be formed onthe underlying gallium nitride layer after vertical growth or lateralgrowth, and need not function as a mask.

[0028] It will also be understood that lateral growth in two dimensionsmay be used to form an overgrown gallium nitride semiconductor layer.Specifically, mask 106 may be patterned to include an array of openings107 that extend along two orthogonal directions such as <1{overscore(1)}00> and <11{overscore (20)}>. Thus, the openings can form arectangle of orthogonal striped patterns. In this case, the ratio of theedges of the rectangle is preferably proportional to the ratio of thegrowth rates of the {11{overscore (2)}0} and {1{overscore (1)}01}facets, for example, in a ratio of 1.4:1.

[0029] Referring now to FIG. 4, continued growth of the gallium nitridelayer 108 a causes lateral overgrowth onto the mask 106, to form lateralgallium nitride layer 108 b. Growth conditions for overgrowth may bemaintained as was described in connection with FIG. 3.

[0030] Referring now to FIG. 5, lateral overgrowth is allowed tocontinue until the lateral growth fronts coalesce at interfaces 108 c,to form a continuous gallium nitride layer 108. The total growth timemay be approximately 60 minutes. As shown in FIG. 1, microelectronicdevices may then be formed in regions 108 b. Devices may also be formedin regions 108 a if desired.

[0031] Additional discussion of the methods and structures of thepresent invention will now be provided. As described above, the openings107 in the mask are preferably rectangular stripes that preferablyextend along the <11{overscore (2)}0> and/or <1{overscore (1)}00>directions on the underlying gallium nitride layer 104. Truncatedtriangular stripes having (1{overscore (1)}) slant facets and a narrow(0001) top facet may be obtained for mask openings 107 along the<11{overscore (2)}0> direction. Rectangular stripes having a (0001) topfacet, (11{overscore (2)}0) vertical side faces and (1{overscore (1)}01)slant facets may be grown along the <1{overscore (1)}00> direction. Forgrowth times up to 3 minutes, similar morphologies may be obtainedregardless of orientation. The stripes develop into different shapes ifthe growth is continued.

[0032] The amount of lateral growth generally exhibits a strongdependence on stripe orientation. The lateral growth rate of the<1{overscore (1)}00> oriented stripes is generally much faster thanthose along <11{overscore (2)}0>. Accordingly, it is most preferred toorient the openings 107 so that they extend along the <1{overscore(1)}00> direction of the underlying gallium nitride layer 104.

[0033] The different morphological development as a function of openingorientation appears to be related to the stability of thecrystallographic planes in the gallium nitride structure. Stripesoriented along <11{overscore (2)}0> may have wide (1{overscore (1)}00)slant facets and either a very narrow or no (0001) top facet dependingon the growth conditions. This may be because (1{overscore (1)}01) isthe most stable plane in the gallium nitride wurtzite crystal structure,and the growth rate of this plane is lower than that of others. The{1{overscore (1)}01} planes of the <1{overscore (1)}00> oriented stripesmay be wavy, which implies the existence of more than one Miller index.It appears that competitive growth of selected {1{overscore (1)}01}planes occurs during the deposition which causes these planes to becomeunstable and which causes their growth rate to increase relative to thatof the (1{overscore (1)}01) of stripes oriented along <11{overscore(2)}0>.

[0034] The morphologies of the gallium nitride layers selectively grownon openings oriented along <1{overscore (1)}00> are also generally astrong function of the growth temperatures. Layers grown at 1000° C. maypossess a truncated triangular shape. This morphology may graduallychange to a rectangular cross-section as the growth temperature isincreased. This shape change may occur as a result of the increase inthe diffusion coefficient and therefore the flux of the gallium speciesalong the (0001) top plane onto the {1{overscore (1)}01} planes with anincrease in growth temperature. This may result in a decrease in thegrowth rate of the (0001) plane and an increase in that of the{1{overscore (1)}01}. This phenomenon has also been observed in theselective growth of gallium arsenide on silicon dioxide. Accordingly,temperatures of 1100° C. appear to be most preferred.

[0035] The morphological development of the gallium nitride regions alsoappears to depend on the flow rate of the TEG. An increase in the supplyof TEG generally increases the growth rate of the stripes in both thelateral and the vertical directions. However, the lateral/verticalgrowth rate ratio decrease from 1.7 at the TEG flow rate of 13 μmol/minto 0.86 at 39 μmol.min. This increased influence on growth rate along<0001> relative to that of <11{overscore (2)}0> with TEG flow rate maybe related to the type of reactor employed, wherein the reactant gasesflow vertically and perpendicular to the substrate. The considerableincrease in the concentration of the gallium species on the surface maysufficiently impede their diffusion to the {1{overscore (1)}01} planessuch that chemisorption and gallium nitride growth occur more readily onthe (0001) plane.

[0036] Continuous 2 μm thick gallium nitride layers 108 may be obtainedusing 3 μm wide stripe openings 107 spaced 7 μm apart and oriented along<1{overscore (1)}00>, at 1100° C. and a TEG flow rate of 26 μmol/min.The overgrown gallium nitride regions 108 b may include subsurface voidsthat form when two growth fronts coalesce. These voids may occur mostoften using lateral growth conditions wherein rectangular stripes havingvertical {11{overscore (2)}0} side facets developed.

[0037] The coalesced gallium nitride 108 layer may have amicroscopically flat and pit-free surface. The surfaces of the laterallygrown gallium nitride layers may include a terrace structure having anaverage step height of 0.32 nm. This terrace structure may be related tothe laterally grown gallium nitride, because it is generally notincluded in much larger area films grown only on aluminum nitride bufferlayers. The average RMS roughness values may be similar to the valuesobtained for the underlying gallium nitride layers 104.

[0038] Threading dislocations, originating from the interface betweenthe gallium nitride underlayer 104 and the buffer layer 102 b, appear topropagate to the top surface of the vertical gallium nitride layer 108 awithin the openings 107 of the mask 106. The dislocation density withinthese regions is approximately 10⁹ cm⁻². By contrast, threadingdislocations do not appear to readily propagate to in the overgrownregions 108 b. Rather, the overgrown gallium nitride regions 108 bcontain only a few dislocations. These few dislocations may be formedparallel to the (0001) plane via the extension of the vertical threadingdislocations after a 90° bend in the regrown region. These dislocationsdo not appear to propagate to the top surface of the overgrown GaNlayer.

[0039] As described, the formation mechanism of the selectively growngallium nitride layer is lateral epitaxy. The two main stages of thismechanism are vertical growth and lateral growth. During verticalgrowth, the deposited gallium nitride grows selectively within the maskopenings 107 more rapidly than it grows on the mask 106, apparently dueto the much higher sticking coefficient, s, of the gallium atoms on thegallium nitride surface (s=1) compared to on the mask (s˜1). Since theSiO₂ bond strength is 799.6 kJ/mole and much higher than that of Si-N(439 kJ/mole), Ga-N (103 kJ/mole), and Ga-O (353.6 kJ/mole), Ga or Natoms should not readily bond to the mask surface in numbers and for atime sufficient to cause gallium nitride nuclei to form. They wouldeither evaporate or diffuse along the mask surface to the opening 107 inthe mask or to the vertical gallium nitride surfaces 108 a which haveemerged. During lateral growth, the gallium nitride grows simultaneouslyboth vertically and laterally over the mask from the material whichemerges over the openings.

[0040] Surface diffusion of gallium and nitrogen on the mask may play aminor role in gallium nitride selective growth. The major source ofmaterial appears to be derived from the gas phase. This may bedemonstrated by the fact that an increase in the TEG flow rate causesthe growth rate of the (0001) top facets to develop faster than the(1{overscore (1)}01) side facets and thus controls the lateral growth.

[0041] The laterally grown gallium nitride 108 b bonds to the underlyingmask 106 sufficiently strongly so that it generally does not break awayon cooling. However, lateral cracking within the SiO₂ may take place dueto thermal stresses generated on cooling. The viscosity (ρ) of the SiO₂at 1050° C. is about 10^(15.5) poise which is one order of magnitudegreater than the strain point (about 10^(14.5) poise) where stressrelief in a bulk amorphous material occurs within approximately sixhours. Thus, the SiO₂ mask may provide limited compliance on cooling. Asthe atomic arrangement on the amorphous SiO₂ surface is quite differentfrom that on the GaN surface, chemical bonding may occur only whenappropriate pairs of atoms are in close proximity. Extremely smallrelaxations of the silicon and oxygen and gallium and nitrogen atoms onthe respective surfaces and/or within the bulk of the SiO₂ mayaccommodate the gallium nitride and cause it to bond to the oxide.

[0042] Accordingly, regions 108 b of lateral epitaxial overgrowththrough mask openings 107 from an underlying gallium nitride layer 104may be achieved via MOVPE. The growth may depend strongly on the openingorientation, growth temperature and TEG flow rate. Coalescence ofovergrown gallium nitride regions to form regions with both extremelylow densities of dislocations and smooth and pit-free surfaces may beachieved through 3 μm wide mask openings spaced 7 μm apart and extendingalong the <1{overscore (1)}00> direction, at 1100° C. and a TEG flowrate of 26 μmol/min. The lateral overgrowth of gallium nitride via MOVPEmay be used to obtain low defect density regions for microelectronicdevices.

[0043] In the drawings and specification, there have been disclosedtypical preferred embodiments of the invention and, although specificterms are employed, they are used in a generic and descriptive senseonly and not for purposes of limitation, the scope of the inventionbeing set forth in the following claims.

That which is claimed:
 1. A method of fabricating a gallium nitridesemiconductor layer comprising the steps of: masking an underlyinggallium nitride layer with a mask that includes an array of openingstherein; and growing the underlying gallium nitride layer through thearray of openings and onto the mask to thereby form an overgrown galliumnitride semiconductor layer.
 2. A method according to claim 1 whereinthe growing step is followed by the step of forming microelectronicdevices in the overgrown gallium nitride semiconductor layer.
 3. Amethod according to claim 1 wherein the growing step comprises the stepof growing the underlying gallium nitride layer through the array ofopenings and onto the mask until the grown gallium nitride layercoalesces on the mask to form a continuous overgrown monocrystallinegallium nitride semiconductor layer.
 4. A method according to claim 1wherein the growing step comprises the step of growing the underlyinggallium nitride layer using metalorganic vapor phase epitaxy.
 5. Amethod according to claim 1 wherein the masking step is preceded by thestep of forming the underlying gallium nitride layer on a substrate. 6.A method according to claim 5 wherein the forming step comprises thesteps of: forming a buffer layer on a substrate; and forming theunderlying gallium nitride layer on the buffer layer opposite thesubstrate.
 7. A method according to claim 1 wherein the masking stepcomprises the step of. masking the underlying gallium nitride layer witha mask that includes an array of stripe openings therein, the stripeopenings extending along a <1{overscore (1)}00> direction of theunderlying gallium nitride layer.
 8. A method according to claim 1wherein the underlying gallium nitride layer includes a predetermineddefect density, and wherein the step of growing the underlying galliumnitride layer through the array of openings and onto the mask to therebyform an overgrown gallium nitride semiconductor layer comprises thesteps of: vertically growing the underlying gallium nitride layerthrough the array of openings while propagating the predetermined defectdensity; and laterally growing the underlying gallium nitride layer fromthe array of openings onto the mask to thereby form an overgrown galliumnitride semiconductor layer of lower defect density than thepredetermined defect density.
 9. A method according to claim 1 whereinthe growing step comprises the step of growing the underlying galliumnitride layer using metalorganic vapor phase epitaxy of triethylgalliumat 13-39 μmol/min and ammonia at 1500 sccm at a temperature of 1000°C.-1100° C.
 10. A method according to claim 7 wherein the growing stepcomprises the step of growing the underlying gallium nitride layer usingmetalorganic vapor phase epitaxy of triethylgallium at 26 μmol/min andammonia at 1500 sccm at a temperature of 1100° C.
 11. A method offabricating a gallium nitride semiconductor layer comprising the stepsof: laterally growing an underlying gallium nitride layer to therebyform a laterally grown gallium nitride semiconductor layer; and formingmicroelectronic devices in the laterally grown gallium nitridesemiconductor layer.
 12. A method according to claim 11 wherein thelaterally growing step comprises the step of laterally growing theunderlying gallium nitride layer until the laterally grown galliumnitride layer coalesces to form a continuous laterally grownmonocrystalline gallium nitride semiconductor layer.
 13. A methodaccording to claim 11 wherein the laterally growing step comprises thestep of laterally growing the underlying gallium nitride layer usingmetalorganic vapor phase epitaxy.
 14. A method according to claim 11wherein the laterally growing step comprises the step of laterallyovergrowing the underlying gallium nitride layer.
 15. A method accordingto claim 11 wherein the underlying gallium nitride layer includes apredetermined defect density, and wherein the laterally growing stepcomprises the step of: laterally growing the underlying gallium nitridelayer to thereby form a laterally grown gallium nitride semiconductorlayer of lower defect density than the predetermined defect density. 16.A gallium nitride semiconductor structure comprising: an underlyinggallium nitride layer; a patterned layer that includes an array ofopenings therein, on the underlying gallium nitride layer; a verticalgallium nitride layer that extends from the underlying gallium nitridelayer and through the array of openings; and a lateral gallium nitridelayer that extends from the vertical gallium nitride layer onto thepatterned layer opposite the underlying gallium nitride layer.
 17. Astructure according to claim 16 further comprising: a plurality ofmicroelectronic devices in the lateral gallium nitride layer.
 18. Astructure according to claim 16 wherein the lateral gallium nitridelayer is a continuous monocrystalline gallium nitride semiconductorlayer.
 19. A structure according to claim 16 further comprising asubstrate, and wherein the underlying gallium nitride layer is on thesubstrate.
 20. A structure according to claim 19 further comprising abuffer layer between the substrate and the underlying gallium nitridelayer.
 21. A structure according to claim 16 wherein the patterned layerincludes an array of openings therein, the openings extending along a<1{overscore (1)}00> direction of the underlying gallium nitride layer.22. A structure according to claim 16 wherein the underlying galliumnitride layer includes a predetermined defect density, wherein thevertical gallium nitride layer includes the predetermined defectdensity, and wherein the lateral gallium nitride semiconductor layer isof lower defect density than the predetermined defect density.
 23. Amonocrystalline gallium nitride layer of a predetermined defect density,including a plurality of spaced apart regions of lower defect densitythan the predetermined defect density.
 24. A layer according to claim 23wherein the predetermined defect density is at least 10⁸ cm⁻² andwherein the lower defect density is less than 10⁴ cm⁻².
 25. A layeraccording to claim 23 wherein the spaced apart regions are stripes thatextend along a <1{overscore (1)}00> direction of the layer.
 26. Agallium nitride semiconductor structure comprising: an underlyinggallium nitride layer; a lateral gallium nitride layer that extends fromthe underlying gallium nitride layer; and a plurality of microelectronicdevices in the lateral gallium nitride layer.
 27. A structure accordingto claim 26 further comprising: a vertical gallium nitride layer betweenthe underlying gallium nitride layer and the lateral gallium nitridelayer.
 28. A structure according to claim 26 wherein the lateral galliumnitride layer is a continuous monocrystalline gallium nitridesemiconductor layer.
 29. A structure according to claim 26 furthercomprising a substrate, and wherein the underlying gallium nitride layeris on the substrate.
 30. A structure according to claim 29 furthercomprising a buffer layer between the substrate and the underlyinggallium nitride layer.
 31. A structure according to claim 26 wherein theunderlying gallium nitride layer includes a predetermined defectdensity, and wherein the lateral gallium nitride semiconductor layer isof lower defect density than the predetermined defect density.